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copyright ? cirrus logic, inc. 2007 (all rights reserved) http://www.cirrus.com 192 khz stereo dac with 2 vrms line out features ? multi-bit delta-sigma modulator ? 24-bit resolution ? supports sample rates up to 192 khz ? 106 db a-wt dynamic range ? -93 db thd+n ? integrated line driver ? 2 vrms output into 5 k ? ac load ? analog low-pass filter ? stereo mutes with auto-mute function ? low clock-jitter sensitivity ? low-latency digital filtering ? popguard ? technology for control of clicks and pops ? single-ended outputs ? +3.3 v core, +9 to 12 v analog, and +1.5 to 3.3 v interface power supplies ? low power consumption ? 20-pin tssop, lead-free assembly description the cs4352 is a complete stereo digital-to-analog sys- tem including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-em- phasis, analog filtering, and on-chip 2 vrms line-level driver. the advantages of this architecture include ideal differential linearity, no distortion mechanisms due to re- sistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. the cs4352 is available in a 20-pin tssop package in both commercial grade (-40c to +85c) and automo- tive grade (-40c to +105c). the cdb4352 customer demonstration board is also available for device evalu- ation and implementation suggestions. please see ?ordering information? on page 20 for complete details. these features are ideal fo r cost-sensitive, 2-channel audio systems including video game consoles, dvd players, a/v receivers, se t-top boxes, digital tvs and dvd recorders, mini-component systems, and mixing consoles. pcm serial interface interpolation filter serial audio input left and right mute controls 2 vrms line level right channel output 2 vrms line level left channel output reset 1.5 v to 3.3 v hardware configuration level translator hardware control multibit ? modulator 3.3 v 9 v to 12 v interpolation filter amp + filter amp + filter multibit ? modulator auto speed mode detect dac dac external mute control internal voltage reference jun '07 ds684f2 cs4352 confidential draft 6/18/07
2 ds684f2 cs4352 table of contents 1. pin descriptions .......................................................................................................... ................... 3 2. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 4 recommended operating conditions .................................................................................... 4 absolute maximum ratings ...................................................................................................... .. 4 dac analog characteristics - commercial (-czz) ............................................................. 5 dac analog characteristics - automotive (-dzz) .............................................................. 6 combined interpolation & on-chip analog filter response .......... ................ .............. 7 switching specifications - serial audio interface .............. ............. ............. ........... 8 digital characteristics ....................................................................................................... ....... 9 power and thermal characteristics ................................................................................... 9 3. typical connection diagram ................................................................................................. .. 10 4. applications ............................................................................................................... .................... 11 4.6.1 capacitor placement ...... ............................................................................................... ........ 13 4.7.1 power-up ................................................................................................................ .............. 14 4.7.2 power-down .............................................................................................................. ............ 14 4.7.3 discharge time .......................................................................................................... ........... 14 5. digital filter response plots ......... ................ ................ ................ ................ .............. .. 16 6. parameter definitions ...................................................................................................... .......... 18 7. package dimensions ........................................................................................................ ........... 19 8. ordering information ...................................................................................................... ......... 20 9. revision history ........................................................................................................... ................. 20 list of figures figure 1.serial input timing .................................................................................................. ...................... 8 figure 2.typical connection diagram ........................................................................................... ............ 10 figure 3.i2s, up to 24-bit data ............................................................................................... ................... 12 figure 4.right-justified data ................................................................................................. .................... 12 figure 5.left-justified up to 24-bit data ....... .............................................................................. ............... 12 figure 6.de-emphasis curve .................................................................................................... ................ 13 figure 7.single-speed stopband rejection ...................................................................................... ........ 16 figure 8.single-speed transition band ......................................................................................... ........... 16 figure 9.single-speed transition band (detail) ................................................................................ ........ 16 figure 10.single-speed passband ripple ........................................................................................ ........ 16 figure 11.double-speed stopband rejection ..................................................................................... ...... 16 figure 12.double-speed transition band .............. .......................................................................... ......... 16 figure 13.double-speed transition ba nd (detail) ............................................................................... ...... 17 figure 14.double-speed passband ripple ........................................................................................ ....... 17 figure 15.quad-speed stopband rejection ....................................................................................... ...... 17 figure 16.quad-speed transition band .......................................................................................... ......... 17 figure 17.quad-speed transition band (detail) ................................................................................. ...... 17 figure 18.quad-speed passband ripple .......................................................................................... ....... 17 list of tables table 1. cs4352 auto-detect ................................................................................................... ................ 11 table 2. single-speed mode standard frequencies ............................................................................... .11 table 3. double-speed mode standard frequencies ............................................................................... 11 table 4. quad-speed mode standard frequencies . ................................................................................ 11 table 5. digital interface format ............................................................................................. .................. 12
ds684f2 3 cs4352 1. pin descriptions pin name pin # pin description sdin 1 serial audio data input ( input ) - input for two?s complement serial audio data. sclk 2 serial clock ( input ) - serial clock for the serial audio interface. lrck 3 left / right clock ( input ) - determines which channel, left or right , is currently active on the serial audio data line. mclk 4 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vd 5 digital power ( input ) - positive power supply for the digital section. gnd 6 16 ground ( input ) - ground reference. dif0 dif1 8 7 digital interface format ( input ) - defines the required relationship between the left/right clock, serial clock, and serial audio data. dem 9 de-emphasis ( input ) - selects the standard 15 s/50 s digital de-emphasis filter response for 44.1 khz sample rates rst 10 reset ( input ) - powers down the device and resets all inte rnal registers to their default settings when enabled. va 11 low voltage analog power ( input ) - positive power supply for the analog section. vbias 12 positive voltage reference ( output ) - positive reference voltage for the internal dac. vq 13 quiescent voltage ( output ) - filter connection for internal quiescent voltage. va_h 17 high voltage analog power ( input ) - positive power supply for the analog section. vl 20 serial audio interface power ( input ) - positive power for the serial audio interface bmutec amutec 14 19 mute control ( output ) - control signal for optional mute circuit. aoutb aouta 15 18 analog outputs ( output ) - the full-scale analog line output level is specified in the analog characteris- tics table. sdin vl sclk amutec lrck aouta mclk va_h vd gnd gnd aoutb dif1 bmutec dif0 vq dem vbias rst va 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 13 14 15 16
4 ds684f2 cs4352 2. characteristics a nd specifications recommended operating conditions (gnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) operation at or beyond these limits may result in permane nt damage to the device. normal operation is not guar- anteed at these extremes. parameters symbol min typ max units dc power supply high voltage analog power low voltage analog power digital power interface power v a_h v a v d v l 8.40 3.13 3.13 1.43 9 3.3 3.3 1.5 12.6 3.47 3.47 3.47 v v v v ambient operating temperature (power applied) -czz -dzz t a -40 -40 - - +85 +105 c c parameters symbol min max units dc power supply high voltage analog power low voltage analog power digital power interface power v a_h v a v d v l -0.3 -0.3 -0.3 -0.3 14.0 3.63 3.63 3.63 v v v v input current, any pin except supplies i in -10ma digital input voltage digital interface v in-l -0.3 v l + 0.4 v ambient operating temperature (power applied) t a -55 +125 c storage temperature t stg -65 +150 c
ds684f2 5 cs4352 dac analog characteristi cs - commercial (-czz) test conditions (unless otherwise specified): t a = 25 c, va_h = 9 v, va = 3.3 v, vd = 3.3 v gnd = 0 v; vbias+ and vq capacitors as shown in figure 2 on page 10 ; input test signal is a 997 hz sine wave at 0 dbfs; measure- ment bandwidth 10 hz to 20 khz. notes: 1. one-half lsb of triangular pdf dither is added to data. parameter symbol min typ max unit all speed modes fs = 48, 96, and 192 khz dynamic range (note 1) 24-bit a-weighted unweighted 16-bit a-weighted unweighted 100 97 - - 106 103 98 95 - - - - db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - - -93 -83 -43 -93 -75 -35 -89 -77 -37 - - - db db db db db db idle channel noise / signal-to-noise ratio (a-wt) - 106 - db interchannel isolation (1 khz) - 99 - db analog output - all modes full scale output voltage 1.84 2.00 2.11 vrms common mode voltage v q -4-vdc max current draw from an aout pin i outmax - 575 - a max current draw from vq i qmax -1- a interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c output impedance z out -50- ? ac-load resistance r l 5--k ? load capacitance c l --100pf
6 ds684f2 cs4352 dac analog characteristic s - automotive (-dzz) test conditions (unless otherwise specified): t a = -40c to 85c, va_h = 9 v, va = 3.3 v, vd = 3.3 v gnd = 0 v; vbias+ and vq capaci tors as shown in figure 2 on page 10 ; input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth 10 hz to 20 khz. notes: 2. one-half lsb of triangular pdf dither is added to data. parameter symbol min typ max unit all speed modes fs = 48, 96, and 192 khz dynamic range (note 2) 24-bit a-weighted unweighted 16-bit a-weighted unweighted 96 93 - - 106 103 98 95 - - - - db db db db total harmonic distortion + noise (note 2) 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - - -93 -83 -43 -93 -75 -35 -89 -73 -33 - - - db db db db db db idle channel noise / signal-to-noise ratio (a-wt) - 106 - db interchannel isolation (1 khz) - 99 - db analog output - all modes full scale output voltage 1.81 2.00 2.17 vrms common mode voltage v q -4-vdc max current draw from an aout pin i outmax -575- a max current draw from vq i qmax -1- a interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c output impedance z out -50- ? ac-load resistance r l 5--k ? load capacitance c l - - 100 pf
ds684f2 7 cs4352 combined interpolation & on-c hip analog filter response (the filter characteristics have been normalized to the sample rate (fs) and can be referenced to the desired sam- ple rate by multiplying the given charac teristic by fs. amplitude vs. frequency plots of the data in the table below are available in ?digital filter response plots? on page 16 .) notes: 3. response is clock-dependent and will scale with fs. 4. for single-speed mode, the measurement bandwidth is from stopband to 3 fs. for double-speed mode, the measurement bandwidth is from stopband to 3 fs. for quad-speed mode, the measurement bandwidth is from stopband to 1.34 fs. 5. de-emphasis is available only in single-speed mode. parameter min typ max unit combined digital and on-chip analog filt er response - single-speed mode - 48 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 4) 102 - - db total group delay (fs = output sample rate) - 9.4/fs - s intra-channel phase deviation - - 0.56/fs s inter-channel phase deviation - - 0 s de-emphasis error (note 5) (relative to 1 khz) fs = 44.1 khz - - 0.14 db combined digital and on-chip analog filt er response - double-speed mode - 96 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .583 - - fs stopband attenuation (note 4) 80 - - db total group delay (fs = output sample rate) - 4.6/fs - s intra-channel phase deviation - - 0.03/fs s inter-channel phase deviation - - 0 s combined digital and on-chip analog filter response - quad-speed mode - 192 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .635 - - fs stopband attenuation (note 4) 90 - - db total group delay (fs = output sample rate) - 4.7/fs - s intra-channel phase deviation - - 0.01/fs s inter-channel phase deviation - - 0 s
8 ds684f2 cs4352 switching specificatio ns - serial audio interface parameters symbol min max units mclk frequency 1.024 48.0 mhz mclk duty cycle 45 55 % input sample rate (auto selection) single-speed mode double-speed mode quad-speed mode fs fs fs 4 84 170 54 108 216 khz khz khz lrck duty cycle 40 60 % sclk pulse width low t sclkl 20 - ns sclk pulse width high t sclkh 20 - ns sclk period single-speed mode t sclkw -- double-speed mode t sclkw -- quad-speed mode t sclkw -- sclk rising to lrck edge delay t slrd 20 - ns sclk rising to lrck edge setup time t slrs 20 - ns sdin valid to sclk rising setup time t sdlrs 20 - ns sclk rising to sdin hold time t sdh 20 - ns sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 1. serial input timing 1 128 () fs --------------------- - 1 64 () fs ------------------ 2 mclk -----------------
ds684f2 9 cs4352 digital characteristics power and thermal characteristics notes: 6. current consumption increases with increasing fs and increasing mclk. typ and max values are based on highest fs and highest mclk. variance between speed modes is small. 7. power down mode is defined as rst pin = low with all clock and data lines held static low. all digital inputs have a weak pull-do wn which is only present during reset. opposing this pull-down will slightly increase the power-down current (pull-down is equivalent to a 50 k ? resistor per pin). 8. valid with the recommended capacitor values on vq and v bias as shown in the typical connection dia- gram in section 3 . parameters symbol min typ max units high-level input voltage v l = 3.3 v v l = 2.5 v v l = 1.5 v v ih v ih v ih 2.0 1.7 1.05 - - - - - - v v v low-level input voltage v l = 3.3 v v l = 2.5 v v l = 1.5 v v il v il v il - - - - - - 0.8 0.7 0.38 v v v input leakage current i in --10 a input capacitance - 8 - pf maximum mutec drive current - 2 - ma mutec high-level output voltage v oh -va_h- v mutec low-level output voltage v ol -0- v parameters symbol min typ max units power supplies power supply current normal operation, v a_h = 12 v (note 6) v a_h = 9 v v a = 3.3 v v d = 3.3 v interface current v l = 3.3 v power-down state, all supplies (note 7) i a_h i a_h i a i d i l i pd - - - - - - 12 10 3 12 0.02 380 21 16 4 16 0.09 - ma ma ma ma ma a power dissipation (all supplies) (note 6) va_h = 12 v normal operation power-down (note 7) va_h = 9 v normal operation power-down (note 7) - - - - 121 1 91 1 158 - 122 - mw mw mw mw power supply rejection ratio (note 8) (1 khz) (60 hz) psrr - - 60 60 - - db db
10 ds684f2 cs4352 3. typical connection diagram digital audio source vl g n d mclk vd aouta 0.1 f 10 f +3.3 v * mode configuration sdin dif1 dif0 dem optional mute circuit rst bmutec 3.3 f left out vbias+ vq lrck sclk 3.3 f 10 k ? 560 ? aoutb 3.3 f va_h 0.1 f 10 f g nd 0.1 f +1.5 v to vd +9 v to +12 v amutec va 0.1 f 10 f +3.3 v 5.1 ?? 2.2 nf* *optional *shown value is for fc=130 khz *remove this supply if optional resistor is present. the decoupling caps should remain. 1 2 3 4 20 10 7 8 9 6 15 5 11 12 17 19 18 optional mute circuit right out 3.3 f 10 k ? 560 ? 2.2 nf* 14 15 13 figure 2. typical connection diagram cs4352
ds684f2 11 cs4352 4. applications 4.1 sample rate range/ope rational mode detect the device operates in one of three operational mo des. the allowed sample rate range in each mode is auto-detected. the cs4352 will auto-detect th e correct mode when the input sample rate (fs), defined by the lrck fre- quency, falls within one of the ranges illu strated in table 1 . sample rates outside the specified range for each mode are not supported. table 1. cs4352 auto-detect 4.2 system clocking the device requires external generati on of the master (mclk), left/right (lrck) and serial (sclk) clocks. the left/right clock, defined also as the input sample rate (f s ), must be synchronously derived from the mclk according to specified ratios. the specified rati os of mclk to lrck, along with several standard au- dio sample rates and the required mc lk frequency, ar e illustrated in tables 2 - 4 . refer to section 4.3 for the required sclk timing associated wit h the selected digital interface format and to ?switching specifications - serial audio interface? on page 8 for the maximum allowed clock frequencies. table 2. single-speed mode standard frequencies table 3. double-speed mode standard frequencies table 4. quad-speed mode standard frequencies input sample rate (f s ) mode 4 khz - 54 khz single-speed mode 84 khz - 108 khz double-speed mode 170 khz - 216 khz quad-speed mode sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 sample rate (khz) mclk (mhz) 128x 192x 256x 176.4 22.5792 33.8688 45.1584 192 24.5760 36.8640 49.1520
12 ds684f2 cs4352 4.3 digital interface format the device will accept audio samples in 1 of 4 digital interface format s, as illustrated in table 5 . the desired format is selected via th e dif1 and dif0 pins. for an illustration of th e required relationship between the lrck, sclk and sdin, see figures 3 - 5 . for all formats, sdin is valid on the rising edge of sclk. also, sclk must have at least 32 cycles per lr ck period in format 2 and 48 cycles per lrck period in format 3. for more information about serial audio formats, refer to cirrus logic ap plication note an282: the 2-chan- nel serial audio interface: a tutorial , available at www.cirrus.com . table 5. digital interface format figure 3. i2s, up to 24-bit data figure 4. right-justified data figure 5. left-justifi ed up to 24-bit data dif1 dif0 descript ion format figure 00 i2s, up to 24-bit data 0 3 01 right-justified, 24-bit data 1 4 10 left-justified, up to 24-bit data 2 5 11 right-justified, 16-bit data 3 4 lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb lsb lrck sclk left channel sdin -6 -5 -4 -3 -2 -1 -7 +1 +2 +3 +4 +5 msb right channel lsb msb +1 +2 +3 +4 +5 lsb -6 -5 -4 -3 -2 -1 -7 msb lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 lsb msb lsb
ds684f2 13 cs4352 4.4 de-emphasis control the device includes on-c hip digital de-emphasis. figure 6 shows the de-emphasis curve for fs equal to 44.1 khz. the frequency response of the de-emphasis curve scales with changes in sample rate, fs. the de-emphasis error will incr ease for sample rate s other than 44.1 khz when pulled to vl, the dem pin activates the 44.1 kh z de-emphasis filter. when pulled to gnd, the dem pin turns off the de-emphasis filter. note: de-emphasis is only availa ble in single-speed mode. 4.5 recommended power-up sequence 1. hold rst low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropria te frequencies, as discussed in section 4.2 . in this state, vq will re- main low and vbias will be connected to va. 2. bring rst high. the device will remain in a low power state with vq low and will initiate th e power-up sequence after approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double- speed mode, and 2048 lrck cycl es in quad-speed mode). 4.6 grounding and power supply arrangements as with any high-resolution converter, the cs4352 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. figure 2 shows the recommended power ar- rangements, with va_h, va, vd, and vl connected to cl ean supplies. if the ground planes are split between digital ground and analog ground, the gnd pins of the cs4352 should be connected to the analog ground plane. all signals, especially clocks, should be kept away from the vbias and vq pins in order to avoid unwanted coupling into the dac. 4.6.1 capacitor placement decoupling capacitors should be placed as close to the dac as possible, with the low-value ceramic ca- pacitor being the closest. to further minimize imped ance, these capacitors should be located on the same layer as the dac. if desired, all supply pins may be connected to the same supply, but a decoupling ca- pacitor should still be placed on each supply pin. note: all decoupling capacitors should be referenced to analog ground. the cdb4352 evaluation board demonstrates the op timum layout and power supply arrangements. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 6. de-emphasis curve
14 ds684f2 cs4352 4.7 popguard transient control the cs4352 uses a novel technique to minimize the ef fects of output transients during power-up and power- down. this technology, when used with external dc-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by si ngle-ended, single-supply converters. it is activat- ed inside the dac when the rst pin is toggled and requires no other external control, aside from choosing the appropriate dc-blocking capacitors. 4.7.1 power-up when the device is initially po wered-up, the audio outputs, aout a and aoutb, are clamped to gnd. following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies- cent voltage. approximat ely 10,000 lrck cycles late r, the outputs reach v q and audio output begins. this gradual voltage rampin g allows time for the external dc-blocki ng capacitors to charge to the quies- cent voltage, minimizing audible power-up transients. 4.7.2 power-down to prevent audible transients at pow er-down, the device must first ente r its power-down state. when this occurs, audio output ceases, and the internal out put buffers are disconnected from aouta and aoutb. in their place, a soft-start current sink is substitute d that allows the dc-blocki ng capacitors to slowly dis- charge. once this charge is dissipa ted, the power to the device may be turned off, and the system is ready for the next power-on. 4.7.3 discharge time to prevent an audio transient at the next power-on, the dc-blocking capacitors must fully discharge be- fore turning on the power or exiting the power-down st ate. if full discharge does not occur, a transient will occur when the audio outputs are initially clamped to gnd. the time that the dev ice must remain in the power-down state is related to the value of the dc-b locking capacitance and the output load. for example, with a 3.3 f capacitor, the minimum power-do wn time will be approximately 0.4 seconds. 4.8 mute control the mute control pins go active during power-up initia lization, reset, muting, or if the mclk to lrck ratio is incorrect. these pins are intended to be used as control for external mute ci rcuits to prevent the clicks and pops that can occur in any single-ended, single-supply system. use of the mute control function is not mandatory but recommended for designs requiring the absolute min- imum in extraneous clicks and pops. also, use of the mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. please see the cdb4352 data sheet for a suggested mu te circuit for dual-supply systems. alternately, the fet muting circuit from the cs4351 data sheet may be used as well. this fet circuit must be placed in series after the rc filter; otherwise noise may occur during muting conditions. fu rther esd protection will need to be taken into consideration for the fet used.
ds684f2 15 cs4352 4.9 initialization and powe r-down sequence diagram user: apply power wait state user: apply mclk, sclk, and lrck mclk/lrck ratio detection user: remove lrck or mclk user: change mclk/lrck ratio analog output is generated user: apply rst user: apply mclk, sclk, lrck, and release rst power-down state vq and outputs low vq and outputs ramp down vq and outputs ramp up
16 ds684f2 cs4352 5. digital filter respon se plots 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 7. single-speed stopband rejectio n figure 8. single-speed transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 9. single-speed transition band (detail) figure 10. single-speed passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 11. double-speed stopband rejection figure 12. double-speed transition band
ds684f2 17 cs4352 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 13. double-speed transition band (det ail) figure 14. double-speed passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 15. quad-speed stopband rejection figure 16. quad-speed transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 17. quad-speed transition band (detail) figure 18. quad-speed passband ripple
18 ds684f2 cs4352 6. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-no ise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion comp onents are below the noise level and do not effect the measurement. this measurement tec hnique has been accepted by the audio engineering society, aes17- 1991, and the electronic industries association of ja pan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right ch annels. measured for each c hannel at the converter's output with all zeros to the input under test and a full-sca le signal applied to the other channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. intra-channel phase deviation the deviation from linear phase within a given channel. inter-channel phase deviation the difference in phase between channels.
ds684f2 19 cs4352 7. package dimensions 1. ?d? and ?e1? are reference datums and do not inclu ded mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/in trusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not re- duce dimension ?b? by more than 0. 07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2 , 3 d 0.252 0.256 0.259 6.40 6.50 6.60 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- -- 0.026 -- -- 0.65 l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. parameters symbol min typ max units package thermal resistance 20l tssop ja -72-c/watt 20l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
20 ds684f2 cs4352 8. ordering information 9. revision history release changes pp1 lowered v a_h minimum specification. updated idle channel nois e specification to a-wt. updated aout current draw specification. updated v il for vl=1.5v. f1 updated performance specifications and limits based on statistical data. f2 added automotive grade specifications and ordering information. updated commercial grade idle channel noise specification. lowered v il maximum specifcation. updated power supply current specification. updated mclk maximum specification. product description package pb-free grade temp range container order # cs4352 20-pin, 192 khz stereo dac with 2 vrms line out 20-pin tssop yes commercial -40 to +85 c rail tape & reel cs4352-czz cs4352-czzr automotive -40 to +105 c rail tape & reel cs4352-dzz CS4352-DZZR cdb4352 cs4352 evaluation board - - - - cdb4352 contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military a pplications, products s urgically implanted into the body, automotive sa fety or security de- vices, life support products or other cri tical applications. inclus ion of cirrus products in s uch applications is under- stood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and prod uct names in this document may be trademarks or service marks of their respective owners.

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